With its high carrier mobility and ultra-thin single atom body thickness, graphene is an ideal material for use in high-speed electronic devices. In graphene-based transistors, a portion of the graphene forms a channel(s) of the device with an electron source and an electron drain located on opposite ends of the channel(s). The channel is typically separated from a gate of the device by a gate dielectric. When a metal gate is used, a high-k material with a relative dielectric constant (k) more than that of silicon oxide, such as hafnium dioxide may be used as the gate dielectric. In fact, it has been found that graphene-based transistors exhibit improved performance when a high-k gate dielectric is used. Namely, graphene-based transistors with high-k gate dielectrics have improved electrical performance. This improved performance is because, for a given dielectric thickness, with high-k dielectrics the gate electrode can achieve a better electrostatic control over the channel as compared with conventional silicon oxide gate dielectrics, thus improving the gating efficiency.
It is, however, very difficult to deposit high-k gate dielectric materials directly onto graphene. In most cases, a high-k dielectric deposited directly onto graphene will not adhere to the graphene. It has been found that using an organic buffer material between the graphene and the high-k gate dielectric improves the adhesion. The use of such organic buffers has been reported and discussed in the literature. See, for example, Farmer et al., “Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors,” Nano Letters, vol. 9, no. 12, pgs. 4474-4478 (2009).
Further, in the fabrication of top-gated graphene-based transistors, the source/drain contacts and the gate electrodes are composed of metal and are usually formed in two separate steps. This fabrication involves two independent lithographic exposures, and inevitably leads to alignment uncertainties between the gate and source/drain contact, the amount of which depends on the lithographic resolution and alignment accuracy. This misalignment between the gate and source/drain contact can have a detrimental impact on the device performance as well as introduce variation between different devices due to the uncontrolled nature of the misalignment.
Thus, techniques for efficient and cost-effective production-scale implementation of an organic buffer adherence layer for top-gated graphene-based transistor fabrication with reduced production variability would be desirable.